RISC-V Out-of-Order CPU
A Tomasulo-style processor that supports RV32I and RV32M execution.
- Built a pipelined front end with fetch, instruction caching, decode, rename, and dispatch.
- Used reservation stations and a reorder buffer to schedule work and retire instructions in order.
- Created constrained-random SystemVerilog testbenches and debugged waveforms with VCS and Verdi.

